View ML2721_5670091.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

january, 2000 preliminary datasheet the ML2721 can be used as a single chip digital cordless telephone transceiver or general purpose frequency shift keying (fsk) radio transceiver. it is designed to work in the 902 to 928mhz ism band under fcc part 15 regulations. the device integrates all the frequency generation, receive and transmit functions for data rates up to 1.5mbps. a complete radio only requires the addition of an antenna switch. micro linear?s ml2751 is an integrated 100mw power amplifier and receive lna with transmit/receive pin diode drivers, and it can be used with the ML2721 for extended range capability. the ML2721 contains a proprietary low if receiver with all channel selectivity. an image reject mixer brings the 915mhz rf signal down to a low if frequency of 1.024mhz. then all if filtering, if gain, and demodulation is performed at 1.024mhz. this provides all the benefits of direct conversion to baseband and minimizes the need for rf filtering. also, the ML2721 can operate with either a low cost lc filter or a saw filter. a single 1.83ghz synthesizer is used for both the receiver lo and the transmitter. the ML2721 transmitter modulates the vco with filtered data, and a driver amplifier provides typically 0dbm at 915mhz. the vco and pll incorporate the resonator, the active devices, and the tuning circuitry for a completely integrated function. an internal post detection filter and data slicer are also included. the ML2721 contains its own dc regulation which allows the ic to operate over a wide power supply voltage range. it also has a simple baseband interface for transmit power management, pll control and detection, and rssi (receiver signal strength indication). single chip 900mhz radio transceiver fully integrated filters for all if, fm discriminator and data filtering image reject mixer & proprietary low if architecture reduce the need for rf filtering integrated 1.83ghz frequency synthesizer with internal vco resonator tx/rx calibration for max power transmission modulation compensation for improved sensitivity performance pll programmed via 3-wire interface dc regulation for 2.7v to 5.0v operation (ic performance is reduced from 2.7v to 3.2v) pll lock detect output analog received signal strength indication (rssi) output to baseband ic easily upgradable for extended range with ml2751 general description ML2721 low if digital cordless transceiver features applications 900mhz dsss cordless phones 900 to 930mhz radio transceivers with ranges from 10 feet to 1000 feet and data rates to 1.5mbps single ic 900mhz low power radio fcc part 15 compliant radio links portable computer/pda tdd and tdma radios preliminary
ML2721 2 january, 2000 preliminary datasheet preliminary table of contents micro linear makes no representations or warranties with respect to the accuracy, utility, or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. no license, express or implied, by estoppel or otherwise, to any patents or other intellectual property rights is granted by this document. the circuits contained in this document are offered as possible applications only. particular uses or applications may invalidate some of the specifications and/or product descriptions contained herein. the customer is urged to perform its own engineering review before deciding on a particular application. micro linear assumes no liability whatsoever, and disclaims any express or implied warranty, relating to sale and/or use of micro linear products including liability or warranties relating to merchantability, fitness for a particular purpose, or infringement of any intellectual prop erty right. micro linear products are not designed for use in medical, life saving, or life sustaining applications. ? micro linear 2000. is a registered trademark of micro linear corporation. all other trademarks are the property of their respective owners. products described herein may be covered by one or more of the following u.s. patents: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; 5,652,479; 5,661,427; 5,663,874; 5,672,959; 5,689,167; 5,714,897; 5,717,798; 5,742,151; 5,747,977; 5,754,012; 5,757,174; 5,767,653; 5,777,514; 5,793,168; 5,798,635; 5,804,950; 5,808,455; 5,811,999; 5,818,207; 5,818,669; 5,825,165; 5,825,223; 5,838,723; 5.844,378; 5,844,941. japan: 2,598,946; 2,619,299; 2,704,176; 2,821,714. other patents are pending. general description ............................................................................................................ ....................................... 1 features ....................................................................................................................... ............................................... 1 applications ................................................................................................................... ............................................ 1 simplified block diagrams ...................................................................................................... ................................... 3 block diagram .................................................................................................................. ......................................... 4 pin configuration .............................................................................................................. ......................................... 5 pin descriptions ............................................................................................................... .......................................... 5 functional description ......................................................................................................... ...................................... 8 introduction ................................................................................................................. ............................................. 8 circuit block descriptions ................................................................................................... ..................................... 8 modes of operation ............................................................................................................. ..................................... 10 overview ..................................................................................................................... ............................................ 10 receive modes ................................................................................................................ ........................................ 10 transmit mode ................................................................................................................ ......................................... 12 standby mode ................................................................................................................. ......................................... 15 test mode .................................................................................................................... ............................................ 15 control interfaces ............................................................................................................. .......................................... 16 register information ......................................................................................................... ........................................ 17 transmit and receive data interfaces ......................................................................................... ............................. 22 applications ................................................................................................................... ............................................ 23 electrical characteristics ..................................................................................................... ....................................... 24 electrical tables .............................................................................................................. ........................................... 24 absolute maximum ratings ....................................................................................................... ................................. 24 operating conditions ........................................................................................................... ...................................... 24 physical dimensions ............................................................................................................ ...................................... 28 ordering information ........................................................................................................... ....................................... 28 warranty
ML2721 3 january, 2000 preliminary datasheet preliminary simplified block diagrams general purpose fsk radio 900mhz dsss cordless phone application image reject mixer ML2721 if circuits control logic pll baseband ic rrfi dout din rssi ref ld clk, data, en xcen, rxon, pllen 3 vcca tx data filter loop filter battery and protection circuits vtune qpo quadrature divide by 2 1.83ghz vco tx rf buffer trfo 3 antenna image reject mixer ML2721 if circuits control logic pll baseband ic ml2751 rrfi rrfo tps feen paon dout din rssi ref ld clk, data, en xcen, rxon, pllen 3 vcca tx data filter loop filter battery and protection circuits vtune qpo quadrature divide by 2 1.83ghz vco tx rf buffer tx rf pa + driver trfo trfi tpa 2 3 rf switch drivers rf pin diode switch antenna pinb pin lc filter lc filter
ML2721 4 january, 2000 preliminary datasheet preliminary block diagram 23 trfo address decode lo 6-bit swallow counter prescalar control lock detect lo 6-bit counter prescalar 32 / 33 reference divider lo phase/ frequency detector lo charge pump control logic tx data filter quadrature divide by 2 1 xcen 2 rxon 3 pllen 30 din 4 en 5 data 6 clk 28 rssi 9 ref 7 ld data slicer data filter demod if filter test mux filter align rssi 32 dout tx rf buffer i q i q 15 vtune 11 qpo 8 vss 12 gnd 17 gnd 16 gnd 19 gnd 20 gnd 18 gnd 25 gnd 21 rrfi 24 vcc 5 dc regulators 22 rvcc 4 14 rvcc 3 10 rvcc 1 31 vdd 29 rvcc 7 27 rvcc 6 13 vcc 2 26 vbg rx quadrature mixers 1.83ghz vco limiter limiter
ML2721 5 january, 2000 preliminary datasheet preliminary pin descriptions pin configuration power & ground 13 vcc 2 i (analog) dc power supply input to the vco voltage regulator 24 vcc 5 i (analog) dc power supply input to voltage regulators and unregulated loads: 2.7 to 5.0v. vcc 5 is the main (or master) analog vcc pin. there must be a capacitor to ground from this pin to decouple (bypass) noise and to stabilize the regulator 16 gnd i (analog) dc ground for vco and lo circuits 10 rvcc 1 o (analog) dc power supply decoupling point for the pll dividers, phase detector, and charge pump. this pin is connected to the output of the regulator and to the pll supplies. there must be a capacitor to ground from this pin to decouple (bypass) noise and to stabilize the regulator 14 rvcc 3 o (analog) dc power supply decoupling point for the vco. connected to the output of the vco regulator. there must be a capacitor to ground from this pin to decouple (bypass) noise and to stabilize the regulator 22 rvcc 4 o (analog) dc power supply decoupling point for the lo chain. connected to the output of a regulator. there must be a capacitor to ground from this pin to decouple (bypass) noise and to stabilize the regulator 27 rvcc 6 o (analog) dc power supply decoupling point for quadrature mixer and if filter circuits. there must be a capacitor to ground from this pin to decouple (bypass) noise and to stabilize the regulator pin # signal name i/o description vcc 5 trfo rvcc 4 rrfi gnd gnd gnd gnd 1 2 3 4 5 6 7 8 9 10111213141516 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 xcen rxon pllen en data clk ld/tpq vss ref rvcc 1 qpo gnd vcc 2 rvcc 3 vtune gnd dout vdd din rvcc 7 rssi/tpi rvcc 6 vbg gnd top view ML2721 32-pin tqfp (h32-7)
ML2721 6 january, 2000 preliminary datasheet preliminary pin descriptions (continued) power & ground (continued) 29 rvcc 7 o (analog) dc power supply decoupling point for if, demodulator, and data slicer circuits. there must be a capacitor to ground from this pin to decouple (bypass) noise and to stabilize the regulator 25 gnd i (analog) dc ground to if, demodulator, and data slicer circuits 12 gnd i (analog) ground for the pll dividers, phase detector, and charge pump 17 gnd i (analog) signal ground for rf small signal circuits. pins 17, 18, and 19 should have short, direct connections to each other and additional connections to ground 18 gnd i (analog) ground return for the receive rf input 19 gnd i (analog) signal ground for the receive mixers 20 gnd i (analog) dc and signal ground for the transmit rf output buffer 31 vdd i (analog) dc power supply input to the interface logic and control registers. this supply is not internally connected to any other supply pin, but its voltage must be less than or equal to the vcc 5 supply, and greater than 2.7v. there must be a capacitor to ground from this pin to decouple (bypass) noise and to stabilize the regulator 8 vss i (digital) ground for digital i/o circuits and control logic transmit/receive 21 rrfi i (analog) receive rf input. nominal impedance at 902 to 928mhz is 50 , with a simple matching network required for optimum noise figure. this input is to the base of an npn transistor and should be ac coupled 23 trfo o (analog) tr ansmit rf output. a broadband 50 output which sources 0dbm over the 902 to 928mhz range. this output is an emitter follower and should be ac coupled data 30 din i (cmos) transmit data input. drives the transmit pulse shaping circuits. serial digital data on this pin becomes fsk modulation on the transmit rf output. data timing is controlled by the logic timing on this pin. the modulation deviation is determined by internal circuits. this is a standard cmos input referenced to vdd &vss 32 dout o ( cmos) serial digital output after demodulation, chip rate filtering and center data slicing. a cmos level output (vss to vdd) with controlled slew rates. a low drive output designed to drive a pcb trace and a cmos logic input while generating minimal rfi. in digital test modes this pin becomes a test access port controlled by the serial control bus mode control and interface lines 1 xcen i (cmos) enables the bandgap reference and voltage regulators when high. consumes only leakage current in standby mode when low. this is a cmos input, and the thresholds are referenced to vdd & vss 2 rxon i (cmos) switches the tr ansceiver between transmit and receive modes. circuits are powered up and signal paths reconfigured according to the operating mode. this is a cmos input, and the thresholds are referenced to vdd & vss pin # signal name i/o description
ML2721 7 january, 2000 preliminary datasheet preliminary mode control and interface lines (continued) 3 pllen i (cmos) enables the pll at the beginning of a transmit or receive slot. goes low before data is received or transmitted. rxon and pllen define four distinct operating modes. this is a cmos input, and the thresholds are referenced to vdd & vss 7 ld/tpq o (cmos) the lock detect output is an open drain output that goes low when the pll is in frequency lock. in analog test modes this pin and the rssi output become test access points controlled by the serial control bus 9 ref i input for the 6.144mhz or 12.288mhz reference frequency. this is used as the reference frequency for the pll, and as a calibration frequency for the on chip filters. this is a self-biased cmos input that is designed to be driven either by a an ac coupled sine wave source (recommended coupling capacitor is 470pf) or by a standard cmos output 11 qpo o charge pump output of the phase detector. this is connected to the external pll loop filter 15 vtune i vco tuning voltage input from the pll loop filter. this pin is very sensitive to noise coupling and leakage currents 26 vbg o bandgap reference voltage. decoupled to ground with a 220nf capacitor 28 rssi/tpi o buffered analog rssi output with a nominal sensitivity of 33mv/db. an rf input signal range of ?95 to ?15dbm gives an rssi voltage output of zero to 2.7v. in analog test modes this pin and the ld output become test access ports serial bus signals 4 en i (cmos) enable pin for the three wire serial control bus which sets the operating frequency and programmable options. the control registers are loaded on a low to high transition of the signal. serial control bus data is ignored when it is high. this is a cmos input, and the thresholds are referenced to vdd & vss 5 data i (cmos) serial control bus data. 16 bit words which include programming data and the two bit address of a control register. this is a cmos input, and the thresholds are referenced to vdd & vss 6 clk i (cmos) serial control bus data is clocked in on the rising edge when en is low. this is a cmos input, the thresholds are referenced to vdd & vss pin descriptions (continued) pin # signal name i/o description
ML2721 8 january, 2000 preliminary datasheet preliminary functional description introduction the ML2721 enables the design and manufacture of low cost, high performance digital dsss cordless telephone transceivers. it can also be used as a general purpose 900mhz transceiver. integral to the ML2721 is a low if receiver whose lo port is driven from an internal synthesizer. included are image rejection if filters, limiters, discriminator, data slicers, and baseband lowpass data filters. it also contains internal voltage regulators to protect critical circuits from power supply noise and transmit modulation circuits. the ML2721 has an internal control interface that programs the synthesizer, the mode of operation, the external lna and pa, and provides a convenient and flexible interface to various baseband processors. for power level monitoring an rssi block is included. the ML2721 is designed to transmit and receive 1.536mchips signals in 2.048mhz spaced channels in the 902 to 928mhz ism band. the 1.536mchips rate with a 15 bit spreading code gives a 102.4kb/s data rate and provides a 10db processing gain. in the receive mode the ML2721 is a single conversion low if receiver. the if frequency of 1.024mhz results in an image response in an adjacent channel. an image reject mixer gives sufficient rejection in this channel. all if filtering and demodulation is performed using active filtering, centered at 1.024mhz. the demodulator is followed by a matched bit rate filter and a data slicer. the sliced data is provided to a baseband chip for de- spreading. in the transmit mode the ML2721 uses the receive mode vco and frequency division, with a driver amplifier providing typically 0dbm output to feed the power amplifier. the pll frequency synthesizer loop is opened during the transmit slot, and the vco is directly modulated by low-pass filtered circuits from the internal modulation filter. the frequency generation circuits are an internal vco at 1.83ghz, dividers, a phase comparator and a charge pump for a pll frequency synthesizer. the vco output is divided by two to produce accurate quadrature outputs at 915mhz. no external components are need for the vco. other modes that are available include power down, and receive and transmit calibrate, which are discussed in further detail. circuit block descriptions phase locked loop (pll) and voltage controlled oscillator (vco) the pll synthesizes channel frequencies to a 512khz resolution, which is more finely spaced than the 1.536mhz signal bandwidth. non-overlapping channels are spaced by 2.048mhz where the if filter and image reject mixer give a typical adjacent channel rejection of 25db. there are twelve non-overlapping channels in the 902 to 928mhz ism band. see table 1. the lo pll is programmed via a 3-wire serial control bus. program words are clocked in on the data line (pin 5) by the clk (pin 6), and loaded into the dividers or control circuits when en (pin 4) is asserted. there is no check for error in the program words. once loaded, register contents are preserved regardless of power conditions. the register status and operation is independent of the mode of operation of the pll. the reference signal from an external crystal oscillator at either 6.144mhz or 12.288mhz is fed to a programmable reference divider. the 1.024mhz reference divider output is fed to the lo phase frequency detector. the pll prescaler input comes from the vco at 1.83ghz, so the 1.024mhz comparison frequency gives 512khz frequency resolution at 902 to 928mhz. the output of the lo divider is fed to the lo phase/ frequency detector and subsequently to the charge pump. the dividers and charge pump are disabled during the active slot to save power. table 1. non-overlapping channel frequencies l e n n a h cz h m n i y c n e u q e r f 10 8 6 . 3 0 9 28 2 7 . 5 0 9 36 7 7 . 7 0 9 44 2 8 . 9 0 9 52 7 8 . 1 1 9 60 2 9 . 3 1 9 78 6 9 . 5 1 9 86 1 0 . 8 1 9 94 6 0 . 0 2 9 0 12 1 1 . 2 2 9 1 10 6 1 . 4 2 9 2 18 0 2 . 6 2 9
ML2721 9 january, 2000 preliminary datasheet preliminary lo vco and transmit driver the internal lo vco operates at 1.8 to 1.86ghz, which is two times the lo frequency of 900 to 930mhz. the vco output is divided by 2 to give accurately matched quadrature signals at 915mhz. in receive mode the lo is offset from the wanted signal by +1.024mhz to produce the low if. this 1.024mhz shift is produced by automatically adding an offset of +2 counts to the pll divider programming. in transmit mode the lo is frequency modulated by the transmitted data, using a modulation port of the vco. the vco output is divided by 2 and a driver amplifier typically develops 0dbm at 900 to 930mhz to directly drive an ml2751 power amplifier. transmit data filter and modulation driver logic level nrz signals at din are scaled and filtered by a 5 th -order lowpass filter. the lowpass filter is tuned to give a 1.35mhz 3db point to pass the 1.536mchips transmit data. the filter data is then fed to the internal modulation port of the lo tank circuit. in the transmit closed loop mode the modulation port is held at its midpoint so that the synthesizer locks to the center channel frequency. in the transmit open loop mode the vco is modulated by gaussian filtered data via the vco modulation port. the modulation driver contains scaling circuitry to control the fm deviation over the entire vco tuning range. this circuit is inactive in the receive mode. receive mixers and if chain the receive rf quadrature mixers down-convert the signal to the 1.024mhz receiver if. the input of the mixer is single-ended and matched to 50 by a series inductor. this gives a good terminating impedance for the preceding rf filter. the quadrature outputs of the down converter feed the if filter. the quadrature mixer and if filter together achieve a typical image rejection of 35db. a quadrature combiner for the image reject mixer and a 12 th -order gaussian bandpass filter make up the active if filters. the active filters provide an accurate gaussian characteristic with a 1.408mhz, 3db bandwidth which improves both sensitivity and adjacent channel rejection. the if amplifiers provide the bulk of the receiver ? s gain. an rssi signal is generated by using the outputs of the if amplifiers. the rssi signal is conditioned and sent to the baseband controller. a frequency-to-voltage converter provides highly linear fm demodulation with good data recovery from the low if. data filter and data slicer the fm demodulator is followed by a gaussian lowpass filter whose 768khz cutoff frequency is matched to the transmitted 1.536mchip/s waveform. this gaussian filter is implemented with similar circuits to the if filter, and is shared with the transmit modulation path. the filter output can be ac coupled to the slicer because the spreading code is almost dc balanced. the data slicer signal is output to the baseband processor for timing recovery and decoding. power supply the ML2721 uses multiple voltage regulators to protect sensitive internal circuits from power supply noise. separate regulators supply the pll dividers, rf circuits and if circuits. each of these regulators takes its power from vcc 5 , and supplies power internally to its respective rvcc n pin. external capacitors are required at each rvcc n pin to decouple the outputs of the internal regulators. the vco regulator takes its power from the vcc 2 pin which is normally connected to the rvcc 6 pin. an external decoupling capacitor is also used on the internal bandgap voltage reference to improve the noise performance of the regulators. these regulators are effective at supply voltages from 3.0v to 5.0v. as the vcc 5 supply voltage drops below 3.0v chip performance gradually degrades, but the ML2721 transceiver will maintain the link as long as the supply voltage is greater than 2.7v. circuit block descriptions
ML2721 10 january, 2000 preliminary datasheet preliminary i.f. filter limiting amplifiers ilo receiver rx input qlo rssi agc f v data filter dout rssi figure 1. receiver block diagram modes of operation overview standby: all circuits powered down, except the control interface (static cmos) rxcal: receive calibration. pll lock up time and if filter alignment, prior to receive receive: receiver circuits active txcal: transmit calibration. pll lock up time prior to transmit transmit: pll open loop, modulated rf output available from ic the four operational modes are rxcal, receive, txcal and transmit. they are set by the rxon (pin 2) and pllen (pin 3) control pins. xcen (pin 1) is the chip enable/disable pin and can be set for standby operation. the relationship between the parallel control lines and the mode of operation of the ic is given in table 2. parallel mode control the ML2721 is intended for use in tdd and tdma radios in battery powered equipment. to minimize power consumption it is designed to switch rapidly from a low power mode (standby) to receive or transmit. the ML2721 can also make a quick transition from receive to transmit for tdd operation. prior to transmitting or receiving time should be allowed for the pll to lock up, and in the case of receive, for the if filters to be aligned. the ML2721 operates as a tdd radio on one rf frequency (transmit or receive). the vco frequency changes between receive and transmit functions because of the if frequency. this vco frequency step is automatically performed. table 2. mode selection receive modes rxcal and receive in receive mode, the received signal at 900mhz is down converted, bandpass filtered (if filter), fed to the frequency-to-voltage converter and low-pass filtered. the output of the low-pass filter is fed to the data slicer which outputs nrz digital data. an rssi voltage output indicates the signal level at the output of the if filter. prior to receive mode the ML2721 should be switched to rxcal mode. this is to allow the if filters to be aligned and for the pll to switch frequency and settle to the required frequency for receiving. filter alignment, using the reference frequency input signal ref, in the rxcal mode sets: discriminator center frequency if filter center frequency and bandwidth receiver data low pass filter bandwidth transmit data low pass filter bandwidth in receive mode the programmed center frequency sets the rf channel that will be received. this means the pll center frequency is the programmed rf center frequency plus the if frequency. the frequency offset required for the low frequency if in the rxcal mode is automatically calculated and performed. receiver circuit operation the ML2721 receive chain is a low if receiver using advanced integrated radio techniques to eliminate external if filters and minimize external rf filter requirements. no external support circuitry is required other than supply decoupling and input matching. the precise filtering and demodulation circuits give improved performance over conventional radio designs using external filters. see figure 1. n e c xn o x rn e l l pe d o m 0xx y b d n a t s 111 l a c x r 110 e v i e c e r 10 1 l a c x t 10 0 t i m s n a r t
ML2721 11 january, 2000 preliminary datasheet preliminary the signal flow in receive mode is from the rf input, through an image reject mixer, if filter, hard limiter, frequency to voltage converter, data filter and data slicer. the ML2721 uses a single conversion super heterodyne receiver with a nominal if of 1.024 mhz. an agc subsystem extends the dynamic range of the receiver. the if frequency and filter bandwidths are given in table 3. major features of the receiver are: high dynamic range mixers with 10db noise figure, ? 15dbm ip3, 35db image rejection (typical) 6-pole bandpass if filter, with accurate gaussian to 12db response center frequency 1.024mhz, bandwidth 1.408 mhz (nominal) limiting if amplifiers with >80db gain, and excellent am rejection agc to extend the dynamic range of the integrated filters & rssi logarithmic rssi output from limiter; agc state is information added to give 80db range fm demodulation by a linear f-to-v converter 5-pole low-pass data filter with an accurate gaussian response and 3db cutoff at 768khz (nominal) 2 level data slicer with dc offset removal the output of the receiver is quantized in amplitude (to 1 bit) but there is no internal timing recovery. timing recovery is performed in the external baseband circuits. ilo qlo data filter fcomp f v fref or fref/2 i q cal tone gen tracking counter modes of operation (continued) table 3. filter parameters to division ratio o i t a r n o i s i v i d e c n e r e f e r62 1 r e t e m a r a p0 = 0 d r1 = 0 d r y c n e u q e r f r e t n e c r e t l i f f i6 / f e r2 1 / f e r h t d i w d n a b r e t l i f f i4 . 4 / f e r8 . 8 / f e r r e t l i f a t a d e v i e c e r8 / f e r6 1 / f e r y c n e u q e r f r e t n e c r e t r e v n o c v o t f6 / f e r2 1 / f e r filter alignment in rxcal mode the receiver is not functional. instead, the ML2721 filter alignment function tunes all the internal filters using the reference frequency from the ref pin. see figure 2. the if filter, data filters, and the f-to-v converter all have their frequency responses governed by rc time constants. every capacitor that affects the frequency response includes a binary weighted capacitor array controlled by a 7 bit tuning bus. in rxcal mode a reference tone at the if center frequency is routed to the f-to-v converter. a digital tracking loop then adjusts the tuning word until there is mid-rail output from the f-to-v converter. this tracking loop may take up to 300s to tune the filter when xcen is asserted, but the tracking loop will continue to make small adjustments whenever the ML2721 is in rxcal mode. because all the filters in the chip are tuned in this manner, centering the f-to-v converter sets up the correct center frequencies and bandwidths for all the filters. the ML2721 must be placed in rxcal mode for 300s whenever xcen is asserted to give time for the filters to align completely. data slicer the data slicer is a comparator that is ac coupled to the receive data filter output. the output is logic high or logic low. this circuit is designed to rapidly acquire valid data at the beginning of a received packet of data. the nominal time constant for the ac coupling is 9s. this limits the maximum recommended run length to four ones or zeroes at 1.3mbps. longer run lengths require the use of a more complex external data slicer circuit. data output drive the ML2721 d out pin is designed to drive a pcb trace and a single logic input with controlled slew rates. buffer the output when driving any logic load greater than 5pf ( i.e. , more than an 10 oscilloscope probe or a single cmos logic input pin). figure 2. dual modulus signal divider
ML2721 12 january, 2000 preliminary datasheet preliminary transmit mode txcal and transmit in transmit mode, the vco is directly modulated with filtered fsk transmit data. the pll is disabled or open, with the charge pump output tri-stated. this stops the pll from contending with the applied modulation. the digital transmit data input is generated by external baseband circuits. this input signal is level shifted and filtered by the transmit modulation filter prior to modulating the vco frequency. due to the low leakage current of the charge pump and tank circuit the ML2721 can be in transmit mode for slot lengths of up to 10ms. during rxcal mode the transmit modulation data filter is automatically tuned to remove the need for production alignment. when the ML2721 is powered up (v dd first applied) the tuning information is reset to mid-range. the filter alignment mode should be used after power up or xcen enabled, and prior to transmission. this ensures the modulation filters are aligned to prevent unwanted spurious emissions. prior to transmitting the pll must tune to the intended rf center frequency of the transmission. this occurs in txcal mode. the transmit modulation is disabled and any input on the d in pin is ignored. the transmit output buffer is enabled during txcal mode. to prevent spurious emissions due to the pll locking, any external rxon switch or pa should be disabled during txcal mode. figure 4. transmitter operating cycle transmitter circuit operation the ML2721 transmitter is a 2-fsk transmitter using a directly modulated open loop vco. see figure 3. this type of transmitter is simple, low power, and well suited to a time-slotted system. the transmitter uses the stored vco tuning voltage on the pll loop filter to set the vco frequency for the duration of the transmit slot. the modulation is introduced through a second vco tuning port. this modulation port has a much lower tuning sensitivity than the main tuning port in order to produce the 550khz fsk deviation. compensation circuits stabilize the modulation deviation over the vco tuning range, and internal logic manages the correct transition from txcal to transmit mode. the ML2721 design supports transmit slot lengths up to 10ms, and the time required to set up the transmitter for a new slot (txcal mode) is 70s. the operating cycle of the transmitter starts with txcal mode. see figure 4. the data filter input is zeroed and the pll locks the vco frequency to the desired rf channel center frequency. a cw signal at the selected rf channel frequency comes out of the transmit rf output. when the pllen control line is de-asserted the transmitter starts its transition to transmit mode. the pll charge pump is disabled, leaving the pll loop filter to hold the correct tuning voltage for this channel. the data formatter injects an nrz bipolar data waveform into the transmit data filter. the transmit data filter band-limits this waveform, and feeds it to the modulation compensation circuits. these scale the modulation voltage (depending on the vco tuning voltage) and drive the vco tuning port with figure 3. transmitter block diagram modulation compensation transmit data filter loop filter din vhigh vlow vmid pllen divider 12 p d n modulation port vco tuning port transmit rf output divide by 2 rxon pllen data filter input data filter output vco tuning port voltage output frequency on trfo pin overview (continued)
ML2721 13 january, 2000 preliminary datasheet preliminary the scaled, filtered modulation. the voltage on the modulation port swings above and below its central value to produce 2-fsk modulation on the vco. the modulation filtering is sufficient to meet the fcc occupied bandwidth and out-of-band emissions requirements, and does not introduce significant isi (inter symbol interference). the transmit modulation filter is a 5 th order all-pole filter, designed for minimum differential group delay and good stop band attenuation at greater than 2mhz. the 3db figure 5. transmitter eye diagram table 4. bandwidth as a function of divider ratio bandwidth of the filter is slaved to the reference frequency. see table 4. overview (continued) may be disturbed, and the radio could transmit on an out- of-band signal. to prevent this a comparator monitors the supply voltage and trips a transmitter shutdown latch if the supply voltage drops below 2.6v. this disables the transmitter output buffer. the latch is reset by the next rising edge of rxon so that the radio cannot transmit r e t e m a r a p 6 y b e d i v i d ) 0 = 0 d r ( 2 1 y b e d i v i d ) 1 = 0 d r ( l a n i m o n r e t l i f a t a d t i m s n a r t h t d i w d n a b b d 3 4 . 4 / f e r8 . 8 / f e r nx fcomp/2 divider adder 12 p d fcomp fref plen register 1 bit14...bit3 input signal at n x fcomp/2 if at fcomp 2n f/6 f/12 fcomp nx fcomp vco loop filter divide by 2 figure 6. transmitter low voltage lockout sequence figure 7. phase locked loop in transmit mode rxon transmit r.f. output vcca supply voltage transmit lockout latch pllen 2.65v transmit rf buffer nx fcomp/2 divider adder 12 p d fcomp ref pllen register 1 bit14...bit3 o n 6 or 12 fcomp n fcomp vco loop filter divide by 2 until the next complete transmitter cycle. see figure 6. if the ML2721 is dc powered on with rxon enabled the transmitter buffer will be latched off. this helps prevent unwanted emissions. programming the ML2721 integrated pll. for ease of use, the ML2721 pll is programmed to the set rf center frequency of operation of the radio. see figure 7. the rf output center frequency is half the vco frequency during transmission. the vco is automatically offset by twice the if, to give the correct receive lo frequency, during reception. this guarantees the baseband figure 5 shows an eye diagram recovered from the transmit rf output of the transceiver with a data stream of 1.5mb/s. transmitter lockout (low voltage) the ML2721 transmitter features a low voltage lockout circuit to meet fcc spurious emissions requirements. if the supply voltage drops below 2.5v the vco frequency
ML2721 14 january, 2000 preliminary datasheet preliminary figure 8. phase locked loop in receive mode table 6. receive mode frequency relationships (n+2) fcomp n fcomp/2 divider adder 12 p d fcomp ref pllen register 1 bit14...bit3 input signal at n fcomp/2 if at fcomp 2 n 6 or 12 fcomp vco loop filter 2 circuits do not reprogram the pll for every receive or transmit packet. the pll divide register should be programmed with a binary integer which represents the desired rf channel frequency divided by 0.512 mhz (when using a 6.144 or 12.288mhz reference frequency). when in transmit mode the pll is disabled and the loop opened to allow modulation of the vco. the vco runs at twice the channel frequency, and the transmit rf output is taken from one output of the quadrature divider. the pll locks during txcal mode. the frequency plan for the pll and vco transmit is given in table 5. when in receive mode the pll is disabled to conserve power and prevent pll divider noise from desensitizing the receiver. see figure 8. the pll frequency is set to give a lo frequency equal to the desired rf channel frequency plus the if frequency. the vco signal is divided by two to provide the quadrature lo for the image reject down convert mixer. the pll locks during rxcal mode. table 5. transmit mode frequency relationsships mode of operation (continued) r e t e m a r a pa l u m r o f e u l a vs n o i t i n i f e d r e t s i g e r y c n e u q e r f l e n n a h c f rn 4 2 0 1 n . e g n a r r e d i v i d e t e l p m o c e h t r o f 3 9 0 4 2 6 7 1 n . d n a b m s i z h m 8 2 9 o t 2 0 9 e h t r o f 2 1 8 1 y c n e u q e r f t u p t u o f r t i m s n a r tn ) 2 / p m o c f (z h m 0 3 9 o t 0 0 9 m o r f e g n a r e h t r e v o c o t d e e t n a r a u g o i t a r n o i s i v i d l l pn e s a h p e h t d n a o c v e h t n e e w t e b n o i s i v i d y c n e u q e r f e h t r o t a r a p m o c y c n e u q e r f o c vn p m o c fz h g 6 8 . 1 o t 0 8 . 1 s i e g n a r y c n e u q e r f n o s i r a p m o c l l p) z h m 1 ~ ( p m o c f . ) o p q ( t u p t u o p m u p e g r a h c t a s e s l u p p m u p e g r a h c f o e t a r . 2 1 r o 6 y b d e d i v i d y c n e u q e r f t u p n i f e r n o i t u l o s e r y c n e u q e r f2 / p m o c ft u p t u o f r t i m s n a r t t a r e t e m a r a pa l u m r o f / e u l a vs n o i t i n i f e d r e t s i g e r y c n e u q e r f l e n n a h c f rn 4 2 0 1 n e g n a r r e d i v i d e t e l p m o c e h t r o f 3 9 0 4 2 6 7 1 n d n a b m s i z h m 8 2 9 o t 2 0 9 e h t r o f 2 1 8 1 y c n e u q e r f l e n n a h cn ) 2 / p m o c f (z h m 0 3 9 o t 0 0 9 m o r f e g n a r e h t r e v o c o t d e e t n a r a u g y c n e u q e r f o l ) 2 + n ( ) 2 / p m o c f ( r e x i m r e v i e c e r e h t f o s t r o p o l e h t t a y c n e u q e r f f iz h m 0 . 1 ~y c n e u q e r f l e n n a h c d n a y c n e u q e r f o l n e e w t e b e c n e r e f f i d o i t a r n o i s i v i d l l p2 + n e s a h p e h t d n a o c v e h t n e e w t e b n o i s i v i d y c n e u q e r f e h t r o t a r a p m o c y c n e u q e r f o c v) 2 + n ( p m o c fz h g 6 8 . 1 o t 0 8 . 1 s i e g n a r y c n e u q e r f n o s i r a p m o c l l p) z h m 0 . 1 ~ ( p m o c f ) o p q ( t u p t u o p m u p e g r a h c t a s e s l u p p m u p e g r a h c f o e t a r 2 1 r o 6 y b d e d i v i d y c n e u q e r f t u p n i f e r f n o i t u l o s e r y c n e u q e r f2 / p m o c ft u p t u o f r t i m s n a r t t a
ML2721 15 january, 2000 preliminary datasheet preliminary the ~1mhz frequency shift is achieved by internally adding an offset of +2 counts to the pll divider register value. the relationship between the lo frequency, the programmed rf channel frequency, and the reference frequency in receive mode is given in table 6. vco open and closed loop operation normally the pll is only operational in rxcal and txcal modes, when a closed loop pll is formed. the pll is a conventional single loop integer division pll. the phase comparator has a charge pump output so that an external passive loop filter can be used. the pll dividers support integer main divider ratios between 1024 and 4095, and reference divider ratios of 6 and 12. in receive and transmit modes the pll loop is opened and the stored vco tuning voltage (on the loop filter) maintains the vco at the desired frequency. in open loop modes the pll charge pump is shut off and the pll circuits are shut down to save power. interlock logic manages the start up and shut down of the pll to ensure that the vco frequency is not disturbed in the transition between modes. if better frequency stability is required the rxcl bit in the pll configuration register allows the pll to remain in the closed loop mode during receive mode. the pll loop must be opened in transmit mode, as the pll would otherwise attempt to remove the fm transmit modulation. pll loop filter design the pll loop filter performs a dual function. in the closed loop modes (rxcal and txcal) it acts as a second order loop filter, and in the open loop modes (transmit, receive without rxcl) it holds the vco tuning voltage for the duration of the data slot. the correct loop filter component values are a function of the desired closed loop bandwidth, loop response damping factor charge pump current, vco tuning sensitivity and pll division ratio. the charge pump current, vco tuning sensitivity, and division ratio range are fixed by the on chip circuits, so the only independent variables are the pll ? s closed loop bandwidth and damping factor. the recommended values of 47nf, 360 and 3.3nf give a 50khz closed loop bandwidth and a damping factor of 0.8 for robust closed loop operation. (18nf, 430 and 1.8nf reduce the damping factor to 0.72; 33nf, 390 and 470pf set the damping factor at 0.9). plastic film capacitors are used on the application circuit because of their excellent mode of operation (continued) dielectric absorption and low leakage current. ceramic capacitors can be used, but care should be taken with applications where there is significant thermal or mechanical shock. standby mode in standby the ML2721 transceiver is powered down. the only active circuits are the control interfaces, which are static cmos to minimize power consumption. the serial control interface (& control registers) remain powered up and will accept and retain programming data as long as the digital supply is present. the ML2721 serial control registers should be loaded with control and configuration data before any active mode is selected. the filter alignment registers are reset at power up. test mode special test access circuitry is needed for ic production test and radio debugging because of the rf to digital functionality of the ML2721. two analogue test outputs (rxtpi and rxtpq) are multiplexed with the rssi and lock detect (ld) output pins, and digital test outputs are multiplexed onto the received data output pin (dout). the test multiplexers are controlled by a test register accessed over the serial control bus.
ML2721 16 january, 2000 preliminary datasheet preliminary control interfaces there are two control interfaces: parallel mode control. controlling the mode of operation of the ML2721. refer to the operational modes section for details. serial interface. programing the pll signal and reference dividers, internal test modes, and filter alignment. other signal interfaces to the ic are: receiver data output transmit modulation data input pll lock detect output, to indicate when the on chip pll is in frequency lock receive rf input, the input to the receiver circuits transmit rf output, the output for the modulated rf signal received signal strength output: rssi indicates the power of the received signal reference frequency input for pll dividers table 7. control logic n e c xn o x rn e l l pe m a n e d o me d o m p i h c 0xx f f of f o 10 1 l a c x tp o o l d e s o l c r e z i s e h t n y s t i m s n a r t 10 0 x td e t a l u d o m d n a p o o l n e p o r e z i s e h t n y s t i m s n a r t 111 l a c x rn g i l a r e t l i f d n a p o o l d e s o l c r e z i s e h t n y s e v i e c e r 110 x rn o e v i e c e r bit allocations data words are entered beginning with the msb. the word is divided into a leading 14-bit data field and a 2-bit address field. when the address field has been decoded the destination register is loaded on the rising edge of en. providing less than 16 bits of data will result in unpredictable behavior when en goes high. parallel interface the chip is enabled by the xcen (transceiver enable) signal. the operating mode is set by the two control lines tx/rx (transmit/receive mode) and pllen (pll enable), and the 3 wire serial data bus. the logic for xcen, rxon and pllen is given in table 7.
ML2721 17 january, 2000 preliminary datasheet preliminary table 8. register organization control interfaces and register description (continued) register 0: pll configuration register 14-bit register data 16-bit register data 2-bit register address res. db13 msb b15 db12 b14 db11 b13 db10 b12 db9 b11 db8 b10 db7 b9 db6 b8 db5 b7 db4 b6 db3 b5 db2 b4 db1 b3 db0 b2 adr1 b1 adr0 b0 res. res. res. res. res. res. res. res. res. lol rcxl rd0 qpp 0 0 register 1: rf channel frequency register 14-bit register data 16-bit register data 2-bit register address res. db13 msb b15 db12 b14 db11 b13 db10 b12 db9 b11 db8 b10 db7 b9 db6 b8 db5 b7 db4 b6 db3 b5 db2 b4 db1 b3 db0 b2 adr1 b1 adr0 b0 res. chq11 chq10 chq9 chq8 chq7 chq6 chq5 chq4 chq3 chq2 chq1 chq0 0 1 register 2: filter tuning select and text mode access register 14-bit register data 16-bit register data 2-bit register address tmode db13 msb b15 db12 b14 db11 b13 db10 b12 db9 b11 db8 b10 db7 b9 db6 b8 db5 b7 db4 b6 db3 b5 db2 b4 db1 b3 db0 b2 adr1 b1 adr0 b0 res. res. res. res. res. res. res. dtm2 dtm1 dtm0 atm2 atm1 atm0 1 0 register 3: production register (not for customer use) note: db=data bit, adr=address bit, res.=reserved. 14-bit register data 16-bit register data 2-bit register address res. db13 msb b15 db12 b14 db11 b13 db10 b12 db9 b11 db8 b10 db7 b9 db6 b8 db5 b7 db4 b6 db3 b5 db2 b4 db1 b3 db0 b2 adr1 b1 adr0 b0 res. res. res. res. res. res. res. res. res. res. res. res. res. 1 1 register information a unidirectional three wire serial bus is used to set the ML2721 ? s transceiver parameters and to program the pll circuits. programming is performed by entering 16-bit words into the ML2721 serial interface. four 16-bit registers are partitioned such that 14 bits are dedicated for data to program the operation and 2 bits are used for register addressing. only three of the registers should be used in normal operation. the purpose of each of the registers is: register 0: pll configuration; register 1: pll tuning data; register 2: internal test access; register 3: reserved for production test only. table 8 shows a register map. table 9 provides a detailed diagram of the register organization: table 9a and 9b outline the pll configuration and channel frequency registers, and table 9c displays the filter tuning and test mode register.
ML2721 18 january, 2000 preliminary datasheet preliminary table 9a. register 0 ? pll configuration register table 9b. register 1 ? channel frequency register control interfaces and register description (continued) t i b a t a de m a nn o i t p i r c s e de s u 3 1 b d / ) b s m ( 5 1 bd e v r e s e r ) o r e z ( 0 o t s t i b l l a t e s 2 1 b d / 4 1 bd e v r e s e r 1 1 b d / 3 1 b1 1 q h c t f i h s y c n e u q e r f l l p s t i b t c e l e s y c n e u q e r f l e n n a h c t f i h s y c n e u q e r f e c n e r e f e r f = o i t a r e d i v i d c 2 1 5 . 0 / s k n i s p m u p e g r a h c ; . f e r . q e r f > . g i s . q e r f : 0 0 1 b d / 2 1 b0 1 q h c 9 b d / 1 1 b9 q h c 8 b d / 0 1 b8 q h c 7 b d / 9 b7 q h c 6 b d / 8 b6 q h c 5 b d / 7 b5 q h c 4 b d / 6 b4 q h c 3 b d / 5 b3 q h c 2 b d / 4 b2 q h c 1 b d / 3 b1 q h c 0 b d / 2 b0 q h c 1 r d a / 1 b1 r d at i b s s e r d d a b s m0 = 1 r d a 0 r d a / ) b s l ( 0 b0 r d at i b s s e r d d a b s l1 = 0 r d a t i b a t a de m a nn o i t p i r c s e de s u 3 1 b d / ) b s m ( 5 1 bd e v r e s e r ) o r e z ( 0 o t s t i b l l a t e s 2 1 b d / 4 1 bd e v r e s e r 1 1 b d / 3 1 bd e v r e s e r 0 1 b d / 2 1 bd e v r e s e r 9 b d / 1 1 bd e v r e s e r 8 b d / 0 1 bd e v r e s e r 7 b d / 9 bd e v r e s e r 6 b d / 8 bd e v r e s e r 5 b d / 7 bd e v r e s e r 4 b d / 6 bd e v r e s e r 3 b d / 5 bl o lt f i h s y c n e u q e r f l l p . e v i e c e r r o f z h m 4 2 0 . 1 , t i m s n a r t r o f z h 0 s i t f i h s o l : 0 . e v i e c e r r o f z h 0 , t i m s n a r t r o f z h m 4 2 0 . 1 s i t f i h s o l : 1 2 b d / 4 bl c x r e v i e c e r l a m r o n n i e d o m l l p n o i t a r e p o . e v i e c e r g n i r u d p o o l n e p o l l p : 0 . e v i e c e r g n i r u d p o o l d e s o l c l l p : 1 1 b d / 3 b0 d rt c e l e s y c n e u q e r f e c n e r e f e r . y c n e u q e r f e c n e r e f e r l a n i m o n z h m 4 4 1 . 6 : 0 . y c n e u q e r f e c n e r e f e r l a n i m o n z h m 8 8 2 . 2 1 : 1 0 b d / 2 bp p qy t i r a l o p p m u p e g r a h c l l p . t n e r r u c s k n i s p m u p e g r a h c ; . f e r . q e r f > . g i s . q e r f : 0 . t n e r r u c s e c r u o s p m u p e g r a h c ; . f e r . q e r f < . g i s . q e r f : 1 1 b d a / 1 b1 r d a0 = 1 r d a 0 b d a / ) b s l ( 0 b0 r d a0 = 0 r d a
ML2721 19 january, 2000 preliminary datasheet preliminary table 9c. register 2 ? filter tuning select and test mode register t i b a t a de m a nn o i t p i r c s e de s u 3 1 b d / ) b s m ( 5 1 be d o m tt i b t c e l e s r e t l i f e n u tn o i t a r e p o l a m r o n r o f 0 o t e d o m t t e s 2 1 b d / 4 1 bd e v r e s e r ) o r e z ( 0 o t s t i b l l a t e s 1 1 b d / 3 1 bd e v r e s e r 0 1 b d / 2 1 bd e v r e s e r 9 b d / 1 1 bd e v r e s e r 8 b d / 0 1 bd e v r e s e r 7 b d / 9 bd e v r e s e r 6 b d / 8 bd e v r e s e r 5 b d / 7 b2 m t d s t i b l o r t n o c t s e t l a t i g i d3 1 e l b a t e e s 4 b d / 6 b1 m t d 3 b d / 5 b0 m t d 2 b d / 4 b2 m t a s t i b l o r t n o c t s e t g o l a n a2 1 e l b a t e e s 1 b d / 3 b1 m t a 0 b d / 2 b0 m t a 1 b d a / 1 b1 r d at i b s e e r d d a b s m1 = 1 r d a 0 b d a / ) b s l ( 0 b0 r d at i b s e e r d d a b s l0 = 0 r d a figure 9. serial bus timing for address and data programming clk t s data lsb en t r t f t h t w t ck t se t d msb db13 db11 db0 adr1 adr0 db12 address data (2 bits) register data (14 bits) control interfaces and register description (continued) serial interface data and clock signals are ignored when en is high. when en is low data on the data pin is clocked into a shift register by rising edges on the clk pin. the information is latched when en goes high. this serial interface bus is similar to that commonly found on pll devices. it can be efficiently programmed by either byte or 16-bit word oriented serial bus hardware. the data latches are implemented in static cmos and use minimal power when the bus is inactive. figure 9 and table 10 provide timing and register programming illustrations. table 10. 3-wire bus timing characteristics l o b m y sr e t e m a r a p) s n ( e m i t t r e m i t e s i r t u p n i k c o l c5 1 t f 5 1 t k c 0 5 > t w h t d i w e s l u p m u m i n i m0 0 0 2 t d 5 1 > t e s 5 1 > t s 5 1 > t h e m i t d l o h k c o l c - o t - a t a d5 1 >
ML2721 20 january, 2000 preliminary datasheet preliminary table 14. pll frequency shift table 12. analog test control bits table 13. digital test control bits table 11. main divider control register bit descriptions adr<1:0>, all 4 registers address bits for all registers. the adr<1:0> bits are the lsb of each register. each register is divided into data field and address field. the data field is the leading field, while the last two bits clocked into the register are always the address field. the address field is decoded and the addressed destination register loaded when en goes high. the last 16 bits clocked into the serial bus will be loaded into the register. clocking in less than 16-bits will result in potentially incorrect entry into the register. atm<2:0>, register #2 only analog test control bits. the test mode selected is described in table 12. the performance of the ML2721 is not guaranteed in these test modes. although primarily intended for ic test and debug, they can also help in debugging the radio system. the default (power up) state of these bits is atm<2:0> = <0,0,0>. when a non-zero value is written to the field, the rssi and ld pins become analog test access ports giving access to the outputs of key signal processing stages in the transceiver. during normal operation the atm field should be set to zero. dtm <2:0>, register #2 only digital test control bits. the dtm<2:0> bits function is described in table 13. the performance of the ML2721 is not guaranteed in these test modes. although primarily intended for ic test and debug, they can also help in debugging the radio system. the default (power up) state of these bits is dtm<2:0> = <0,0,0>. when a non-zero value is written to these fields the dout pin becomes a digital test access port for key digital signals in the transceiver. during normal operation the dtm field should be set to zero. chq <11:0>, register #1 only channel frequency selection bits. these bits set the channel frequency for the transceiver. with a 6.144mhz or 12.288mhz input to the ref pin the channel frequency value is calculated by dividing the chq value by 0.512. a 1.024mhz offset is automatically added in the receiver mode to accommodate the if frequency. the recommended operating range value of the chq is from 1,024 (400 hex ) to 4,094 (ffe hex ). these bits should be programmed to a valid channel frequency before xcen is asserted. lol register #0 only pll frequency shift bit. lo shift for transmit and receive. for normal operations, it is recommended that lol = 0. see table 14. control interfaces and register description (continued) power on state all the registers are cleared when voltage is applied to vdd (pin 31). the pll divide ratio (see table 11) and pll configuration registers should be programmed before xcen is asserted for the first time. the divide ratio is calculated as f c /0.512 where f c is the channel frequency in mhz. divide ratio = f c 0.512 a 1.024mhz offset is automatically added in the receive mode. 4 1 b , 5 1 b2 b o t 3 1 b1 b0 b . a . no i t a r e d i v i d l l p01 2 m t a1 m t a0 m t ai p tq p t 000 i s s r) t c e t e d k c o l l l p ( d l 00 1 t c e n n o c o n 010 ) e d o m e v i e c e r ( t u p t u o r e t l i f f i 011 e v i e c e r ( t u p t u o r e x i m d e r e f f u b q ) e d o m 10 0 e v i e c e r ( t u p t u o r e x i m d e r e f f u b f i ) e d o m 10 1 ) s e d o m l l a ( t u p t u o r e t l i f a t a d 110 ) e d o m e v i e c e r ( s t u p t u o r e t i m i l f i 111 . f e r v 7 6 . 1t u p n i t r o p . d o m o c v 2 m t d1 m t d0 m t dt u o d 000 a t a d d e t a l u d o m e d 00 1 e t a t s c g a r e v i e c e r 010 t u p t u o r e d i v i d n i a m l l p 011 t u p t u o r e d i v i d e c n e r e f e r l l p l o lt i m s n a r t r o f t f i h s o le v i e c e r r o f t f i h s o l 00 z h m 4 2 0 . 1 + 1z h m 4 2 0 . 1 +0
ML2721 21 january, 2000 preliminary datasheet preliminary l c x re d o m l l p e v i e c e r 0p o o l n e p o l l p 1p o o l d e s o l c l l p table 16. pll mode in normal receive operation l o lt i m s n a r t r o f t f i h s o le v i e c e r r o f t f i h s o l 00 z h m 4 2 0 . 1 + 1z h m 4 2 0 . 1 +0 table 15. reference frequency select p p qy t i r a l o p p m u p e g r a h c l l p 0 . e c n e r e f e r y c n e u q e r f > l a n g i s y c n e u q e r f . t n e r r u c s k n i s p m u p e g r a h c 1 . e c n e r e f e r y c n e u q e r f > l a n g i s y c n e u q e r f . t n e r r u c s e c r u o s p m u p e g r a h c table 17. pll charge pump polarity control interfaces and register description (continued) res (reserved) all 4 registers these bits are reserved. clear these bits to 0 (zero) for normal operation. when power is reset all of the registers ? data fields are cleared to 0 (zero). rd0 register #0 only reference divide bit zero. this bit sets the reference division of the pll to either 6 or 12. see table 15. rxcl register #0 only receive closed loop bit. this bit is used in receive mode to put the pll into either open loop or closed loop. see table 16. tmode register #2 only this bit is used to activate the automatic filter alignment circuitry. for normal operations this bit must be cleared to 0 (zero). qpp register #0 only this bit sets the charge pump polarity to sink or source current. for a majority of applications this bit is cleared (qpp = 0). for applications where an external amplifier is in the loop filter the bit is set to 1 to change the charge pump polarity. see table 17. register configurations at power up (default) all register values are cleared to 0 (zero). power up is defined as occurring when vdd 2.0v. the register default values are valid 1ns after power up.
ML2721 22 january, 2000 preliminary datasheet preliminary transmit and receive data interfaces the din and dout pins are cmos logic level for serial data that correspond to fsk modulation on the radio channel. the ML2721 is designed to operate as an fsk transceiver in the 902 to 928mhz ism band. the chip rate, bit rate and spreading code are determined in the baseband processor, and the fm deviation and transmit filtering are determined in the transceiver. din provides data to the transmit data filter, which band limits the transmitted chips before they are fm modulated. there is no re-timing of the chips, so the transmitted fsk chips take their timing from the din pin. in the receive chain fm demodulation, data filtering, and data slicing take place in the ML2721 receiver, with chip, bit and word rate timing recovery performed in the baseband processor. rssi, ld, and ref there are three other interface pins between the ML2721 transceiver and the baseband ic: the rssi, ld and ref pins. ref is the master reference frequency for the transceiver. it supplies the frequency reference for the rf channel frequency and the filter tuning. the ref pin is a cmos input with internal biasing resistors. it can be ac coupled through a 470pf coupling capacitor to a sine wave source of between 0.5 and 3.0v peak-to-peak. the ref input can also be driven by a cmos logic output. the pll comparison and the if filter center frequency are both equal to the ref input frequency divided by either 6 or 12, depending on the setting of the rdiv bit in the pll configuration control word. the if filter and data filter bandwidths track the if filter center frequency. the received signal strength indicator (rssi) pin supplies a voltage indicating the amplitude of the received rf signal. it is normally connected to the input of a low speed adc on an external baseband ic, and is used during channel scanning to detect clear channels on which the radio may transmit. the rssi voltage is proportional to the logarithm of the received power level. a voltage of 0v to 2.7v corresponds to an rf input power of ? 95 to ? 15dbm with a nominal slope of 33mv/db. the lock detect (ld) pin is an open drain output that pulses low when the pll is in frequency lock. it is provided to indicate to an external baseband processor that the ML2721 pll is failing to lock to the reference frequency. this output is latched on the falling edge of pllen. the baseband processor can sample ld after de- asserting pllen. in analog test modes the rssi and ld pins become analog test access ports (tpi and tpq, respectively) that allow the user to observe internal signals in the ML2721. rf interfaces the rrfi receive input pin and the trfo transmit output pin are the only rf i/o pins and provide approximately 50 impedance. the rrfi pin requires a simple input matching network for best input noise figure, and the trfo pin is matched to 50 by an ac coupling capacitor. the application circuit shows recommended matching circuit values for the micro linear demonstration pcb, but different values will be needed for other pcb layouts. the associated rf input and output ground pins must have direct connections to an rf ground plane, and the rf block supply pins must be well decoupled from the rf ground pins. control interface (continued)
ML2721 23 january, 2000 preliminary datasheet preliminary the ML2721 operates in the 902 to 928mhz ism band under fcc part 15, section 247 or section 249. for cordless telephone applications under part fcc 15 section 247 the ML2721 and its companion part (ml2751 or ml2752) are used as a direct sequence spread spectrum (dsss) transceiver with chip rates up to 1.6mchips/s. the ML2721 is used alone for short range high data rate applications under fcc part 15 section 249. dsss cordless telephone the ML2721 requires a suitable digital baseband processor to operate in this mode. the baseband processor spreads the digital data (at up to 150kbytes/s) using an 11 to 15 bit chip sequence. this composite baseband signal (at up to 1.6mchips/s) is fed to the ML2721 din input. the ML2721 transmit circuits low pass filter the baseband signal and fm modulate the transmit rf output. the transmitted signal is a direct sequence-fsk signal which meets the fcc requirements for >10db processing gain and a 6db bandwidth >500khz. it is a constant envelope signal which can be amplified in an efficient class c power amplifier without suffering spectral regrowth. the ML2721 receive circuits downconvert, filter, and demodulate the fm signal to recover the original spread spectrum baseband signal. the baseband processor de- spreads this signal and recovers the lower data rate signal with a correlator. to extend the range in this ds-fsk mode the companion ml2751 (or ml2752) part is used. this is a combination transmit power amplifier, receive low noise amplifier, and pin diode driver for 902 to 928mhz ism band applications. low power stand alone the ML2721 can be used without the ml2751/2 as an fsk radio transceiver. only an external pin diode t/r switch and antenna filtering are required. the 0dbm (typical) output makes full use of the fcc part 15, section 247 or section 249 transmitted field strength limits. bit rates from1.0 to1.6mbits/s are feasible. the data slicer achieves full performance with run lengths up to 4 consecutive 1 or 0 bits at 1.3 to 1.6mbits/s (3 consecutive bits at 1mbit/s). this constraint can be met with run length limited coding, which also simplifies the clock recovery circuits. alternatively an external data slicer circuit can be used for longer run lengths. applications
ML2721 24 january, 2000 preliminary datasheet preliminary electrical characteristics electrical tables absolute maximum ratings absolute maximum ratings are those values beyond which the device could be permanently damaged. absolute maximum ratings are stress ratings only and functional device operation is not implied. vdd, vcc 2, vcc 5 .................................................... 6.0v vss, gnd ........................................................... 0 0.3v junction temperature .............................................. 150 c storage temperature range ..................... ? 65 c to 150 c lead temperature (soldering, 10s) .......................... 260 c operating conditions normal temperature range ........................ -10 c to 60 c vdd, vcc 2, vcc 5 range .............................2.7v to 5.5v thermal resistance ( ja ) (note 2) ...................... 100 c/w unless otherwise specified, vcc 5 & vdd = 3.3v, t a = operating temperature range. (note 1) symbol parameter conditions min typ max units power consumption all circuits, sleep mode dc connected, xcen low 10 a supply current, receive mode 40 ma supply current, rx cal mode 48 ma supply current, transmit mode 40 ma supply current, tx cal mode 49 ma vco and lo pll lo output frequency in 512khz steps 91515 mhz phase noise at driver output vco phase locked, loop band width 1.2mhz 50khz. discontinuities, other than ? 100 3mhz reference spurs, not allowed. ? 120 >7mhz ? 125 dbc/hz lo pll reference frequency at phase pll main divider input is at 1.83ghz detector 1.024 mhz lo division range integer pll divider limits 1024 4095 lo charge pump sink/source current 5.5 ma lo lock up time for transmit/receive from pllen asserted frequency change <70 s lo lock up time for channel switch from pllen asserted, any channel change in 902 to 928 mhz band <150 s lo lock up time from sleep from xcen, pll dividers programmed <300 s reference signal input level 6.144 or 12.288mhz sine wave, capacitively coupled 2.0 v p-p receive chain receive rf input noise figure 10 db maximum receive rf input correct demodulation of fsk signal 0 dbm receive rf input ip3 test tones 2 and 4 channels away ? 12 dbm
ML2721 25 january, 2000 preliminary datasheet preliminary electrical tables (continued) symbol parameter conditions min typ max units receive chain (continued) receive conducted emissions from rf ? 50 dbm input receive rf input impedance 900 to 930mhz tbd receive rf mixer image rejection measured at 3.5mhz offset 35 db receive adjacent channels rejection @ ? 80dbm 2.048mhz channel spacing 1 channel 15 2 channels 40 3 or more channels 45 db if filters if filter type, 3db point 6 th order gaussian to 12db if filter center frequency after 300s of realignment 1.024 mhz if filter attenuation at 320khz within 10ms of alignment, 3 db referenced to 1024khz if filter attenuation at 1725khz within 10ms of alignment 3 db referenced to 1024khz limiter, agc and fm demodulator recovery from overload from 0dbm at input <20 s eb/no for 12.5% cer 3 db co-channel rejection,12.5% cer ? 80dbm, modulated with 1.536 mb/s gfsk, bt = 0.5, prbs data 4 db am tolerance, 12.5% cer ? 80dbm, am modulated at 100khz 90 % rssi performance rssi rise time: < ? 100dbm to ? 15dbm into 20pf load, 20% to 80% the if mixer 5s rssi fall time: < ? 15dbm to ? 100dbm into 20pf load, 20% to 80% the if mixer 5s rssi maximum voltage ? 15dbm in 2.8 v rssi minimum voltage no signal 0.05 v rssi sensitivity, mid range 35 mv/db rssi maximum signal sensitivity >50% ? 15 dbm rssi minimum signal sensitivity >50% ? 95 dbm rssi accuracy 3db receiver settling time from pllen low to valid data <50 s receive data filter (note 2) bandwidth 3db 768 khz attenuation >10mhz 60 db transmit rf driver driver amplifier output power into 50 0 dbm driver amplifier output return loss 900 to 930mhz 14 db
ML2721 26 january, 2000 preliminary datasheet preliminary electrical tables (continued) symbol parameter conditions min typ max units transmit modulation modulation deviation, internal vco 5 consecutive 1 or 0 bits 550 khz transmit data filter bandwidth 3db 1.4 mhz attenuation >10mhz 60 db interface logic levels input high voltage vdd ? 0.4 v input low voltage +0.4 v input bias current 0.5 a input capacitance (not tested) 4 pf ld output low voltage sinking 0.1ma <0.4 v dout high voltage sourcing 0.1ma vdd ? 0.4 v dout low voltage sinking 0.1ma 0.4 v dout sink/source current 0.4 ma note 1: limits are guaranteed by 100% testing, sampling, or correlation with worst case test conditions. note 2: filter type is 5 th order gaussian.
ML2721 27 january, 2000 preliminary datasheet preliminary physical dimensions ordering information part number temperature range package ML2721dh ? 10 c to 60 c 32 pin tqfp 7mm body micro linear corporation 2092 concourse drive san jose, ca 95131 tel: (408) 433-5200 fax: (408) 432-0295 www.microlinear.com ds2721-01 0.048 max (1.20 max) seating plane 0.354 bsc (9.00 bsc) 0.276 bsc (7.00 bsc) 1 0.276 bsc (7.00 bsc) 0.354 bsc (9.00 bsc) 9 25 17 0.032 bsc (0.8 bsc) pin 1 id 0.012 - 0.018 (0.29 - 0.45) 0.037 - 0.041 (0.95 - 1.05) 0.018 - 0.030 (0.45 - 0.75) 0.003 - 0.008 (0.09 - 0.20) 0 o - 8 o package: h32-7 32-pin (7 x 7 x 1mm) tqfp

▲Up To Search▲

Price & Availability of ML2721

	To Download ML2721 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .